Design of an LDPC Decoder and Its Performance

Palleti Raju, Potnuru Surya Prasad


Low-Density Parity-Check codes (LDPC) are widely using ECC (Error Correcting Codes) for having eminent capabilities. By using Message Passing Algorithm, these codes can be decoded. These codes perform better than Turbo Codes and easily attains Shannon’s limit. For low SNR, these codes provide low bit error rates. For high SNR, these codes provide no error floor. These codes are used in various applications like Wi-Fi, Mobile WiMAX, DVD-S2, and IEEE 802.3 (10 GBASE –T). The main feature of these codes is that they can provide efficient encoding and decoding. In this paper, an LDPC encoder and decoder are implemented by Verilog techniques. For simulation, Xilinx Vivado 14.2 and Questa Sim 10.4c are used. And for synthesis, Leonardo Spectrum 2014b.4is used. These designs are also implemented on Nexys 4-DDR XC7A100TCSG324-2L FPGA.

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